1. Field of the Invention
The present invention relates to a semiconductor device test system, and more particularly to a semiconductor device test system which extends driver- and comparator-functions acting as important functions of a test header to an external part (e.g., a HIFIX board) of the test header, such that it can double the productivity of a test without upgrading the test header.
2. Description of the Related Art
As well known in the art, a semiconductor device manufactured by a predetermined assembly process or a semiconductor fabrication process experiences a test process for determining whether or not a specific function is finally carried out.
FIG. 1 is a perspective view illustrating a conventional system for testing a semiconductor device. Referring to FIG. 1, the conventional system for testing the semiconductor device includes a test header 2, a handler 3, and a High Fidelity Tester Access Fixture board (HIFIX board) 1. The test header 2 tests a semiconductor device. The handler 3 carries a predetermined number of semiconductor devices, performs a desired test on the semiconductor devices, classifies the semiconductor devices according to their grades, and loads the classified semiconductor devices thereon. The HIFIX board 1 is located between the test header 2 and the handler 3, such that it establishes an electrical connection between the semiconductor device and the test header 2. In other words, if the semiconductor seated in an insert on a test tray is brought into contact with sockets of an (m×n) matrix on the HIFIX board 1 on the condition that the HIFIX board 1 having the sockets of the (m×n) matrix is matched with a test site of the handler 3, the conventional semiconductor test system can simultaneously test (m×n) semiconductor devices.
The HIFIX board is a board used in the process of testing semiconductor products. The HIFIX board comprises a component (connector, pogo pin block) for transmitting an electric signal that is approved from a tester; a PCB for configuring a circuit; a socket for which a device is loaded; a socket guide; a handler; a tester; and an equipment for docking, etc.
FIG. 2 is a block diagram illustrating a conventional semiconductor test header apparatus.
Referring to FIG. 2, the test header2 includes a single test header substrate and a variety of circuit elements mounted on one or both sides of the test header substrate. This test header substrate includes an ALgorithm Pattern Generator (ALPG) 21, a Pin Electronic (PE) unit (not shown), a digital comparator 23, and an interface unit (not shown).
The algorithm pattern generator (ALPG) 21 generates a predetermined test pattern signal for testing the semiconductor. The pin electronic (PE) unit includes: a driver 25 for recording the test pattern signal generated from the algorithm pattern generator (ALPG) 21 in a semiconductor device called a Device Under Test (DUT) 30; and a comparator 27 for comparing a read signal of the test pattern read by the DUT 30 with a reference signal corresponding to characteristics of the corresponding semiconductor and outputting the result of the comparison. The digital comparator 23 determines whether or not there is a failure in the output signal of the pin electronic (PE) unit. The interface unit interfaces with a test controller 10 controlling the semiconductor test system.
In more detail, the pin electronic (PE) unit is a circuit for directly applying current and voltage signals based on test patterns to the semiconductor contained in the DUT 30, such that it forms a single input/output (I/O) channel If the algorithm pattern generator (ALPG) 21 generates the test pattern signal, the driver 25 contained in the PE unit records a corresponding test pattern signal in a test-objective semiconductor contained in the Ball Grid Array (BGA)-type DUT 30. The recorded pattern signal is read by the DUT 30, such that the read pattern signal is outputted to the comparator 27. The comparator 27 transmits a comparison resultant signal indicating the comparison result between the read signal of the test pattern and the reference signal to the digital comparator 23. The digital comparator 23 determines whether or not there is a failure of the corresponding read signal, and transmits the determined result to a test controller 10.
However, in the conventional semiconductor device test system, the handler generally requests a large number of DUTs at once. In recent times, an improved handler capable of simultaneously handling 512 DUTs has been developed and come onto the market, such that a test header for the improved handler must be upgraded. However, a device required for upgrading the above-mentioned test header is very expensive, so that the conventional semiconductor device test system has difficulty in upgrading the test header, and also has difficulty in increasing the productivity.
Needless to say, although the conventional semiconductor device test system can establish a connection between the test header (e.g., a 256-parallel test header) and the handler (e.g., 512-parallel handler) by segmenting one I/O channel into two I/O channels, it takes a long period of time to read the read signals outputted from the DUT as many as the number of segmentations from the test header, resulting in an increased total test time. That is, although the handler of the conventional semiconductor device test system is upgraded such that the improved semiconductor device test system is configured, there is no or little difference in productivity between the conventional semiconductor device test system and the improved semiconductor device test system.